1. Field
The present invention relates to the field of electronics. More specifically, the invention relates to an apparatus, system and method for tracking in-flight instructions in a pipeline.
2. General Background
Prior generation microprocessors feature circuitry arranged to successively fetch and execute instructions. More specifically, this circuitry fetches instruction pointers (IPs) and places these IPs in an instruction pipeline. The "instruction pipeline" generally includes a plurality of processing stages, wherein the first few processing stages are referred to as a "front-end pipeline" and the remaining processing stages are referred to as a "back-end pipeline". Since IPs are loaded into the front-end pipeline and instructions associated with these IPs are subsequently executed at the back-end pipeline, in-flight IPs are subject to self-modifying code (SMC) conflicts.
A "SMC conflict" is a condition where the execution of an instruction of an executable program causes self-modification of that executable program. This self-modification may lead to the execution of "stale" instruction data already progressing through an instruction pipeline. In particular, a SMC conflict may occur for a number of reasons including, for example, those instances when a new instruction is created or when data embedded into an instruction of a repeatedly executable program is modified. Thus, various SMC handling techniques have been adopted over the years.
For example, earlier generation processors, such as i80486.TM. and PENTIUM.RTM. microprocessors produced by Intel Corporation of Santa Clara, Calif., snooped the instruction pipeline for SMC conflicts. This technique is suitable for pipelines having a small number of processing stages and supporting in-order instruction processing. However, these early generation processors are unable to track out-of-order pipelining of instructions.
Another technique, utilized by the PENTIUM.RTM. PRO microprocessor, requires the use of an instruction victim cache (IVC) in combination with a normal instruction cache (I-cache) to guarantee that all of the instructions in the pipeline would be resident in one of these caches. However, this cache architecture requires complicated management logic.
Hence, it would be advantageous to provide a system and method to track in-flight instructions in which the resultant information can be used to detect SMC conflicts for example.